This application claims priority from Provisional Application Ser. No. 60/344,664, filed on Dec. 28, 2001.
The continual demand for enhanced integrated circuit performance has resulted in, among other things, a dramatic reduction of semiconductor device geometries, and continual efforts to optimize the performance of every substructure with any semiconductor device. A number of improvements and innovations in fabrication processes, material composition, and layout of the active circuit levels of a semiconductor device have resulted in very high-density circuit designs. Increasingly dense circuit design has not only improved a number of performance characteristics, it has also increased the importance of, and attention to, semiconductor material properties and behaviors.
Bipolar circuitry, especially that utilized in BiCMOS technologies, requires control of many electrical parameters to achieve optimal performance. Often, controlling the current gain of the bipolar transistor (Hfe) is essential to achieve desired performance levels. Hfe is the ratio of the collector current to the base current in the bipolar transistor. Consider, for example, bipolar power output stages. Such circuitry requires maximization of Hfe to insure adequate current to a load while maintaining an acceptable quiescent operating current. Similarly, bipolar input circuits require a minimum Hfe to insure compliance with input impedance requirements. Maximum Hfe limits are often determined by a technology's operational voltage requirements. Most mass production technologies are developed having 3:1 allowable Hfe ranges (e.g., 40-120, 100-300).
In order for mass-production technologies to be cost-effective, tight parametric control of individual circuits must, to some extent, be compromised. High speed, high volume processing cannot be stopped or slowed to analyze or correct unique, design-related, parametric variations. Often, parametric variations across disparate circuit designs are not addressed during processing, and not identified until finished devices are tested or fail in use. Thus, where possible, parametric variation introduced by circuit design should be minimized.